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248 lines
8.1 KiB
248 lines
8.1 KiB
2 years ago
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/********************************** (C) COPYRIGHT *******************************
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* File Name : port.c
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* Author : WCH
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* Version : V1.0
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* Date : 2022/05/10
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* Description : WCH Qingke V4A FreeRTOS��ֲ�ӿ�
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* SPDX-License-Identifier: Apache-2.0
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*******************************************************************************/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the RISC-V RV32 port.
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*----------------------------------------------------------*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#include "portmacro.h"
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#include "core_riscv.h"
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/* Standard includes. */
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#include "string.h"
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/* Let the user override the pre-loading of the initial LR with the address of
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prvTaskExitError() in case it messes up unwinding of the stack in the
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debugger. */
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#ifdef configTASK_RETURN_ADDRESS
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#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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#else
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#define portTASK_RETURN_ADDRESS prvTaskExitError
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#endif
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/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS
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to use a statically allocated array as the interrupt stack. Alternative leave
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configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
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linker variable names __freertos_irq_stack_top has the same value as the top
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of the stack used by main. Using the linker script method will repurpose the
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stack that was used by main before the scheduler was started for use as the
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interrupt stack after the scheduler has started. */
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#ifdef configISR_STACK_SIZE_WORDS
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static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
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const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
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/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
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the task stacks, and so will legitimately appear in many positions within
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the ISR stack. */
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#define portISR_STACK_FILL_BYTE 0xee
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#else
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/* __freertos_irq_stack_top define by .ld file */
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extern const uint32_t __freertos_irq_stack_top[];
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const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
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#endif
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/*
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* Setup the timer to generate the tick interrupts. The implementation in this
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* file is weak to allow application writers to change the timer used to
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* generate the tick interrupt.
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*/
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void vPortSetupTimerInterrupt( void ) __attribute__(( weak ));
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/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
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stack checking. A problem in the ISR stack will trigger an assert, not call the
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stack overflow hook function (because the stack overflow hook is specific to a
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task stack, not the ISR stack). */
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#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )
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#warning This path not tested, or even compiled yet.
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static const uint8_t ucExpectedStackBytes[] = {
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
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#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
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#else
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/* Define the function away. */
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#define portCHECK_ISR_STACK()
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#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
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/*-----------------------------------------------------------*/
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/* just for wch's systick, don't have mtime */
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void vPortSetupTimerInterrupt( void )
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{
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/* set software is lowest priority */
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PFIC_SetPriority(SWI_IRQn, 0xf0);
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PFIC_EnableIRQ(SWI_IRQn);
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/* set systick is lowest priority */
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PFIC_SetPriority(SysTick_IRQn, 0xf0);
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SysTick_Config(configCPU_CLOCK_HZ / configTICK_RATE_HZ);
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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extern void xPortStartFirstTask( void );
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#if( configASSERT_DEFINED == 1 )
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{
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volatile uint32_t mtvec = 0;
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/* Check the least significant two bits of mtvec are 0b11 - indicating
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multiply vector mode. */
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__asm volatile( "csrr %0, mtvec" : "=r"( mtvec ) );
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configASSERT( ( mtvec & 0x03UL ) == 0x3 );
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/* Check alignment of the interrupt stack - which is the same as the
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stack that was being used by main() prior to the scheduler being
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started. */
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configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
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#ifdef configISR_STACK_SIZE_WORDS
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{
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memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
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}
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#endif /* configISR_STACK_SIZE_WORDS */
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}
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#endif /* configASSERT_DEFINED */
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/* If there is a CLINT then it is ok to use the default implementation
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in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
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configure whichever clock is to be used to generate the tick interrupt. */
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vPortSetupTimerInterrupt();
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{
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/* Enable external interrupts. */
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}
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/* Initialise the critical nesting count ready for the first task. */
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xPortStartFirstTask();
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/* Should not get here as after calling xPortStartFirstTask() only tasks
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should be executing. */
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return pdFAIL;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* Not implemented. */
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for( ;; );
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}
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/*-----------------------------------------------------------*/
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__attribute__((section(".highcode")))
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void SysTick_Handler( void )
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{
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if( xTaskIncrementTick() != pdFALSE )
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{
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portYIELD();
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}
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SysTick->SR &= (~(1<<0));
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}
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/*-----------------------------------------------------------*/
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__HIGH_CODE
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void vPortEnterCritical( void )
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{
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portDISABLE_INTERRUPTS();
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}
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/*-----------------------------------------------------------*/
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__HIGH_CODE
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void vPortExitCritical( void )
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{
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portENABLE_INTERRUPTS();
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}
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extern void SysTick_Handler(void);
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extern void TMR0_IRQHandler(void);
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extern void GPIOA_IRQHandler(void);
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extern void GPIOB_IRQHandler(void);
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extern void SPI0_IRQHandler(void);
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extern void BB_IRQHandler(void);
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extern void LLE_IRQHandler(void);
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extern void USB_IRQHandler(void);
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extern void TMR1_IRQHandler(void);
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extern void TMR2_IRQHandler(void);
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extern void UART0_IRQHandler(void);
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extern void UART1_IRQHandler(void);
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extern void RTC_IRQHandler(void);
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extern void ADC_IRQHandler(void);
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extern void PWMX_IRQHandler(void);
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extern void TMR3_IRQHandler(void);
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extern void UART2_IRQHandler(void);
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extern void UART3_IRQHandler(void);
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extern void WDOG_BAT_IRQHandler(void);
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typedef void (*user_irq_handler_t)(void);
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__attribute__((section("wch_user_vectors")))
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user_irq_handler_t wch_user_irq_table[] =
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{
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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SysTick_Handler, /* SysTick Handler */
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0,
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0, /* SW Handler */
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0,
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/* External Interrupts */
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TMR0_IRQHandler , /* 0: TMR0 */
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GPIOA_IRQHandler, /* GPIOA */
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GPIOB_IRQHandler , /* GPIOB */
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SPI0_IRQHandler , /* SPI0 */
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BB_IRQHandler , /* BLEB */
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LLE_IRQHandler , /* BLEL */
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USB_IRQHandler , /* USB */
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0,
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TMR1_IRQHandler , /* TMR1 */
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TMR2_IRQHandler, /* TMR2 */
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UART0_IRQHandler , /* UART0 */
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UART1_IRQHandler, /* UART1 */
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RTC_IRQHandler, /* RTC */
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ADC_IRQHandler, /* ADC */
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0,
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PWMX_IRQHandler, /* PWMX */
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TMR3_IRQHandler, /* TMR3 */
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UART2_IRQHandler, /* UART2 */
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UART3_IRQHandler, /* UART3 */
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WDOG_BAT_IRQHandler, /* WDOG_BAT */
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};
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__attribute__((section(".highcode")))
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void user_interrupt_handler(uint32_t mcause)
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{
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uint32_t irq_num;
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irq_num = mcause & 0x7f;
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if(wch_user_irq_table[irq_num] != NULL)
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{
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wch_user_irq_table[irq_num]();
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}
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}
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