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/********************************** (C) COPYRIGHT *******************************
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* File Name : startup_ch58x.s
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* Author : WCH
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* Version : V1.0.0
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* Date : 2021/05/10
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* Description : CH583 FreeRTOS启动文件
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* SPDX-License-Identifier: Apache-2.0
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*******************************************************************************/
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.extern unified_interrupt_handler
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.section .init,"ax",@progbits
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.global _start
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.align 1
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_start:
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j handle_reset
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.section .vector,"ax",@progbits
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.align 1
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_vector_base:
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.option norvc;
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.word 0
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.word 0
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.word NMI_Handler /* NMI Handler */
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.word HardFault_Handler /* Hard Fault Handler */
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.word 0xF5F9BDA9 /* boot option, can't modify */
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.word Ecall_M_Mode_Handler /* 5 */
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.word 0
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.word 0
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.word Ecall_U_Mode_Handler /* 8 */
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.word Break_Point_Handler /* 9 */
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.word 0
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.word 0
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.word unified_interrupt_handler /* SysTick Handler */
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.word 0
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.word SW_Handler /* SW Handler */
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.word 0
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/* External Interrupts */
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.word unified_interrupt_handler /* 0: TMR0 */
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.word unified_interrupt_handler /* GPIOA */
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.word unified_interrupt_handler /* GPIOB */
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.word unified_interrupt_handler /* SPI0 */
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.word unified_interrupt_handler /* BLEB */
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.word unified_interrupt_handler /* BLEL */
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.word unified_interrupt_handler /* USB */
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.word unified_interrupt_handler /* USB2 */
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.word unified_interrupt_handler /* TMR1 */
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.word unified_interrupt_handler /* TMR2 */
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.word unified_interrupt_handler /* UART0 */
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.word unified_interrupt_handler /* UART1 */
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.word unified_interrupt_handler /* RTC */
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.word unified_interrupt_handler /* ADC */
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.word unified_interrupt_handler /* I2C */
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.word unified_interrupt_handler /* PWMX */
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.word unified_interrupt_handler /* TMR3 */
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.word unified_interrupt_handler /* UART2 */
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.word unified_interrupt_handler /* UART3 */
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.word unified_interrupt_handler /* WDOG_BAT */
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.option rvc;
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.section .vector_handler, "ax", @progbits
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.weak NMI_Handler
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.weak HardFault_Handler
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.weak Ecall_M_Mode_Handler
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.weak Ecall_U_Mode_Handler
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.weak Break_Point_Handler
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.weak SysTick_Handler
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.weak SW_Handler
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.weak TMR0_IRQHandler
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.weak GPIOA_IRQHandler
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.weak GPIOB_IRQHandler
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.weak SPI0_IRQHandler
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.weak BB_IRQHandler
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.weak LLE_IRQHandler
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.weak USB_IRQHandler
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.weak USB2_IRQHandler
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.weak TMR1_IRQHandler
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.weak TMR2_IRQHandler
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.weak UART0_IRQHandler
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.weak UART1_IRQHandler
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.weak RTC_IRQHandler
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.weak ADC_IRQHandler
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.weak I2C_IRQHandler
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.weak PWMX_IRQHandler
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.weak TMR3_IRQHandler
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.weak UART2_IRQHandler
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.weak UART3_IRQHandler
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.weak WDOG_BAT_IRQHandler
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NMI_Handler: 1: j 1b
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HardFault_Handler: 1: j 1b
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Ecall_M_Mode_Handler: 1: j 1b
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Ecall_U_Mode_Handler: 1: j 1b
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Break_Point_Handler: 1: j 1b
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SysTick_Handler: 1: j 1b
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SW_Handler: 1: j 1b
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TMR0_IRQHandler: 1: j 1b
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GPIOA_IRQHandler: 1: j 1b
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GPIOB_IRQHandler: 1: j 1b
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SPI0_IRQHandler: 1: j 1b
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BB_IRQHandler: 1: j 1b
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LLE_IRQHandler: 1: j 1b
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USB_IRQHandler: 1: j 1b
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USB2_IRQHandler: 1: j 1b
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TMR1_IRQHandler: 1: j 1b
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TMR2_IRQHandler: 1: j 1b
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UART0_IRQHandler: 1: j 1b
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UART1_IRQHandler: 1: j 1b
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RTC_IRQHandler: 1: j 1b
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ADC_IRQHandler: 1: j 1b
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I2C_IRQHandler: 1: j 1b
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PWMX_IRQHandler: 1: j 1b
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TMR3_IRQHandler: 1: j 1b
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UART2_IRQHandler: 1: j 1b
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UART3_IRQHandler: 1: j 1b
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WDOG_BAT_IRQHandler: 1: j 1b
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.section .handle_reset,"ax",@progbits
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.weak handle_reset
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.align 1
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handle_reset:
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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1:
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la sp, _eusrstack
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/* Load highcode code section from flash to RAM */
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2:
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la a0, _highcode_lma
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la a1, _highcode_vma_start
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la a2, _highcode_vma_end
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bgeu a1, a2, 2f
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1:
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lw t0, (a0)
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sw t0, (a1)
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addi a0, a0, 4
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addi a1, a1, 4
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bltu a1, a2, 1b
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/* Load data section from flash to RAM */
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2:
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la a0, _data_lma
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la a1, _data_vma
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la a2, _edata
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bgeu a1, a2, 2f
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1:
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lw t0, (a0)
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sw t0, (a1)
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addi a0, a0, 4
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addi a1, a1, 4
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bltu a1, a2, 1b
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2:
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/* clear bss section */
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la a0, _sbss
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la a1, _ebss
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bgeu a0, a1, 2f
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1:
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sw zero, (a0)
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addi a0, a0, 4
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bltu a0, a1, 1b
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2:
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/* ��ˮ�߿���λ & ��̬Ԥ�����λ */
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li t0, 0x1f
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csrw 0xbc0, t0
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/* ��Ӳ��ѹջ���ر��ж�Ƕ�� */
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li t0, 0x01
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csrw 0x804, t0
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/* ʹ�û���ģʽ����freertos�д��ж� */
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li t0, 0x1800
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csrs mstatus, t0
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la t0, _vector_base
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ori t0, t0, 3
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csrw mtvec, t0
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la t0, main
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csrw mepc, t0
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mret
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